1. Field of the Invention
This invention relates to semiconductor devices, and more particularly to junction field effect transistors. Specifically, the invention is a novel gate induced by ions implanted in a dielectric layer overlying the channel.
2. Description of the Prior Art
A typical junction field-effect transistor (JFET), as seen in FIG. 1, consists of a conductive channel region 1, source 4 and drain 6 contacts, and two gate contacts 8 and 9. In some structures, the top and bottom gates, 2 and 3, are physically connected, and only one gate contact is provided. By varying the reverse bias on the gate-to-source contacts 8 and/or 9 to 4, the cross-section of the channel region 1* is adjusted, affecting source to drain resistance. The cross-sectional area and its resistance determine the amount of current that flows through the device. JFETs are well-known devices which, because of their structure and the fabrication techniques used in their manufacture, have the following detrimental characteristics:
1. The gate junction can be reverse biased, decreasing the current through the device. If the gate junction is forward biased, carriers are injected into the channel, damaging the device.
2. The process of forming the gate junction gives rise to a certain amount of undesirable "burst" or "popcorn" noise, which limits the application of the device.